Current related art techniques for power leakage reduction include multiple voltage threshold (multi-Vt) bias techniques. Such techniques are generally applied during the design process.
In order to save design cost and time to market, semiconductor designers typically use only one platform design to satisfy the feature and performance requirements of many related product applications; in this way, the cost of product development is amortized over many design opportunities. However, this related art approach for accommodating any given customer's intended use or product application results in unwanted power consumption in idle circuits, because the current leakage is a significant part of the total power dissipation.
It is desirable to provide a power leakage reduction technique that addresses the problem of power reduction for a plurality of product variants of a semiconductor device or IC after the device has been designed.